The present invention relates generally to semiconductor device fabrication and, in particular, to methods of fabricating back-end-of-line (BEOL) interconnect structures and BEOL interconnect structures formed by the methods.
In modern electronics, high levels of functionality are achieved on a single chip by integrating large numbers of devices. One process commonly employed in achieving high circuit densities is by using BEOL interconnect structures to link numerous devices, thereby forming a complex integrated circuit. In this way, a wide range of electronic functions, such as central processing units (CPUs), application specific integrated circuits (ASICs), or Radio Frequency Integrated Circuits (RFICs) can be provided on a single chip.
BEOL interconnect structures are routinely fabricated by damascene processes, such as a dual damascene process in which a dielectric layer is deposited, vias and trenches are etched in the dielectric layer, and the vias and trenches are filled with a conductor using a single blanket deposition followed by planarization. This process is replicated to stack different conductive and via levels to create a multi-level, high density framework of conductive interconnections.
As feature sizes shrink with advances in technology node, the dimensions of the interconnect structure spacing and thicknesses of the dielectric layers are correspondingly reduced. Reduced spacing between interconnect structures results in higher levels of capacitive coupling between the structures, which adversely affects circuit performance. For example, higher levels of capacitance between data lines in digital circuitry will introduce cross-talk that lowers the maximum clock speed at which a circuit can operate without introducing bit errors. In another example, parasitic capacitances between BEOL interconnect structures lowers the maximum frequency at which an analog circuit can operate by introducing unwanted phase shifts and attenuation to signals carried by the structures. The problems caused by parasitic capacitance between different metallization levels of BEOL interconnect structures are further exacerbated by higher levels of inductance and resistance that frequently accompany reductions in interconnect structure dimensions.
Improved BEOL interconnect structures and methods for fabricating BEOL interconnect structures are needed that reduce parasitic capacitance between conductors.